FIG. 1 illustrates a prior art memory system. A memory controller 10 and memory module 12 are connected by a memory channel 14 that provides signal lines for the transfer of data between the components. The system may include additional memory modules that may be connected to the controller through channel 14 or to the first module through another memory channel.
The memory controller 10, which may be an integral part of a processor, or part of a chipset 18 that supports a processor, controls the flow of memory data between the processor and memory devices 20 such as dynamic random access memory (DRAM) chips located on the module. In a conventional system, the memory channel 14 is implemented with a bi-directional data bus in which write data is sent to the module over the same signal lines that read data is returned to the controller. Data that is transferred across the channel is typically grouped into frames that include an actual data payload as well as check codes that enable the system to verify data integrity.
In some systems, a memory channel may utilize unidirectional links rather than a bi-directional bus. For example, a memory controller may be connected to a memory module by an outbound path having unidirectional bit lines that transfer information such as write data, address information, control signals, etc., to the module, and an inbound path having unidirectional bit lines that transfer information to the controller. If there is more than one memory module, the controller and modules may be arranged in a ring configuration in which each component may only transmit data in one direction to one other component.